··· lezzter Preis 49.00 ··· 9783844382778 ··· 10361118162 ··· In this thesis leakage reduction techniques like stack forcing, multiple threshold CMOS, variable threshold CMOS are explored, that mitigate leakage in circuits, operating in the active mode at various temperatures. Also, implications of technology scaling on the choice of techniques to mitigate total leakage are closely examined. The result is guidelines for designing low-leakage circuits in nanometer technology nodes. Logic gates in the 180nm, 130nm, 100nm and 70nm technology nodes are simulated and analyzed. Here delay analysis of various logic circuits are also examined. Hersteller: LAP Lambert Academic Publishing Marke: LAP Lambert Academic Publishing EAN: 9783844382778 Kat: Hardcover/Naturwissenschaften, Medizin, Informatik, Technik/Technik/Maschinenbau, Fertigungstechnik Lieferzeit: Print on Demand Versandkosten: Ab 20¤ Versandkostenfrei in Deutschland Icon: https://www.inforius-bilder.de/bild/?I=KqSYSg3P525xYZwQWbGjvh2GVCwWN5CA7hC%2BY7lyG2g%3D Bild:
Affiliate Marketing
AdHoc MeldungenAffiliate & PublisherAdvertiser & MerchantAcademyAntwortenArtikelsucheAdventskalender
AffilitivProduktdatenPreisvergleich
