für 44.10€ kaufen ··· 9783846559130 ··· 1036189306 ··· Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. This thesis introduces a design of a verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification, while retaining the possibility to run verification also in the user-friendly debugging environment of a simulator. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM) as well as assertion-based verification, making its application range quite large. According to the experiments carried out on a prototype implementation, the achieved acceleration is proportional to the number of checked transactions and the complexity of the verified system. The maximum acceleration achieved on the set of experiments was over 130 times. Hersteller: LAP Lambert Academic Publishing Marke: LAP Lambert Academic Publishing EAN: 9783846559130 Kat: Hardcover/Naturwissenschaften, Medizin, Informatik, Technik/Informatik, EDV Lieferzeit: Sofort lieferbar Versandkosten: Ab 20¤ Versandkostenfrei in Deutschland Icon: https://www.inforius-bilder.de/bild/?I=WiGp5QGw2fN0alDRCLOWJUKoeEEMYorMOtxk4b2ZFY8%3D Bild:
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