für 61.20€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray Thermal and power related issues are common in most modern microprocessors. We are not only talking about servers, but also mobile devices, desktop computers, laptop, GPUs, APUs, etc. For many years microprocessor design has been (and is) limited by power dissipation and temperature. Many studies refer to these key factors as the `Power Wall`. Even today, this `Power Wall` is still limiting the number of cores that can be placed on the same die. In this project we worked in the design, implementation and testing of microarchitecture techniques for accurately adapting the processor performance to power constraints in the single core scenario, multi-core scenario and 3D die-stacked core scenario. We first introduce `Power-Tokens`, to approximate the power being consumed by the processor in real time. Later we will discuss different mechanisms based on pipeline throttling, confidence estimation, instruction criticality information, to adapt the processor to a predefined power budget. ····· 1036120457
für 53.10€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray Multiprocessor Systems-on-Chip (MPSoC) offer superior performance while maintaining flexibility and reusability thanks to software oriented personalization. While most MPSoCs are today heterogeneous for better meeting the targeted application requirements, homogeneous MPSoCs may become in a near future a viable alternative bringing other benefits such as run-time load balancing, task migration and dynamic frequency scaling. This book relies on a homogeneous NoC-based MPSoC platform developed for exploring scalable and adaptive on-line continuous mapping techniques. Each processor of this system is compact and runs a tiny preemptive operating system that monitors various metrics and is entitled to take remapping decisions through code migration techniques and dynamic frequency scaling. This approach that endows the architecture with decisional capabilities permits refining application implementation at run-time according to various criteria. ····· 1036119728
für 44.10€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray The main purpose of this project is to design an inverter that will enable the inversion of a DC power source, supplied by Photovoltaic (PV) Cells, to an AC power source that will be either used to supply a load or connected directly to the utility grid. The benefit of this project is to give access to an everlasting and pollution free source of energy. The future is looking towards alternative power sources all of which will need to be regulated in one form or another. To make this possible, a highly efficient low cost product will have to be designed. Among all the different converter designs only a few are capable of providing high power with high efficiency. This will be tested experimentally, first by computer simulation, and then in the laboratory Implementation. ····· 1036118859
für 44.10€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray Robots are not only cost effective but productive enough as compared to human labor. They were promising in decreasing and eliminating factors of accidents in construction sites. These systems are marked advancement in hot weather construction decreasing heavy/hazardous tasks and shorting entire construction duration. Although robots are being extensively used in construction in the present ERA but these robots are being used in constructing the large buildings. While none advancements have been made in house construction. Our main idea is to develop a manipulator type of robot which can assist the construction work to build the walls of houses. The inspiration behind the idea is to develop a rehabilitator in nature s fury and disasters like Floods, Earth quakes, etc. Initially our main focus is on construction of straight walls. The design of this manipulator is generic enough thus it is capable of working in different fields like commercial stores, chemical labs, construction industry, airports, etc. We have also pointed out the area where advancement and changes can be made in the present design to improve its efficency and quality. ····· 1036118274
für 61.20€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray Researchers from both academia and industry agree that future CMPs will accommodate large shared on-chip last-level caches. However, the exponential increase in multicore processor cache sizes accompanied by growing on-chip wire delays make it difficult to implement traditional caches with a single, uniform access latency. Non-Uniform Cache Access (NUCA) designs have been proposed to address this situation. A NUCA cache divides the whole cache memory into smaller banks that are distributed along the chip and can be accessed independently. Response time in NUCA caches does not only depend on the latency of the actual bank, but also on the time required to reach the bank that has the requested data and to send it to the core. So, the NUCA cache allows those banks that are located next to the cores to have lower access latencies than the banks that are further away, thus mitigating the effects of the cache s internal wires. ····· 103613840
für 44.10€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray The power dissipation levels in high performance personal computers continue to increase rapidly while the silicon die temperature requirements remain unchanged or have been lowered. Advanced air cooling solutions for the major heat sources such as central processing unit and graphics processing unit modules uses high flow rate fans to manage the heat load at the expense of significant increases in the sound power emitted by the computer system. Closed loop liquid cooling systems may offer an excellent means to efficiently meet the combined challenges of high heat loads, low thermal resistance, and low noise. This paper describes attributes of an advanced liquid cooling system that can cool heat sources within the computer system. The cooling system described here uses copper cold plates to pick up heat from CPU and highly efficient liquid-to-air heat exchangers to transfer the heat to air by forced convection. A water based coolant is used for high thermal performance and a highly reliable compact pump is used to circulate the fluid in a closed loop. The air cooling used in computers is no longer appropriate to deliver the proper thermal management. ····· 103613781
für 53.10€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray As the complexity of hardware designs is increasing rapidly day-by-day with the introduction of newer technologies, it is very important to ensure the correctness of these designs. During verification, the primary objective is to measure the coverage of the verified functionalities of a design and, hence, indicate the completeness of the verification effort. Since it is widely believed that the future of design verification lies in the co-existence of both simulation and formal property verification techniques, unifying the coverage goals for both of these contrasting verification technologies is becoming very essential. The inter-relationships among the simulation test plans, assertions and test benches are very important to the success of verification, but they are often loosely tied. In this monograph, we attempt to relate then more formally to achieve a potentially better strategy for cohesive coverage management in verification. We believe that the methods presented in this monograph will lead to wider adoption of the cohesive coverage management techniques in the design validation flow. ····· 103613626
für 44.10€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray Lowest-level cache misses are satisfied by the main memory through a specific address mapping scheme that is hard-coded in the memory controller. A dynamic address mapping scheme technique is investigated to provide higher performance and lower power consumption, and a method to throttle memory to meet a specific power budget. Several experiments are conducted on single and multithreaded synthetic memory traces -to study extreme cases- and validate the usability of the proposed dynamic mapping scheme over the fixed one. Results show that applications performance varies according to the mapping scheme used, and a dynamic mapping scheme achieves up to 2x increase in peak bandwidth utilization and around 30% higher energy efficiency than a system using only a single fixed scheme Moreover, the technique can be used to limit memory accesses into a subset of the memory devices by controlling data allocation at a finer granularity, providing a method to throttle main memory by allowing un-accessed devices to be put into power-down mode, hence saving power to meet a certain power budget. ····· 103613610
für 88.20€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray En este trabajo se propone una arquitectura de codificación de vídeo multiestándar eficiente y flexible que puede utilizarse para la implementación de codificadores conformes con los estándares basados en el lazo de codificación híbrido como la Recomendación H.263 o los estándares ISO/IEC 13818-2 (MPEG 2) e ISO/IEC 14496-2 (MPEG 4). En primer lugar, se presenta un estudio exhaustivo de la Recomendación H.263 y de los estándares MPEG-2 y MPEG-4 desde el punto de vista de las tareas que realiza el codificador. En segundo lugar, se propone una arquitectura, MVIP 2, compuesta por un procesador RISC y procesadores especializados en las diferentes tareas de codificación que utiliza tres niveles de secuenciamiento (de pel, de macrobloque y de imagen). En tercer lugar, se presenta una realización de MVIP 2 para codificación de vídeo H.263 que se prototipa sobre una plataforma basada en FPGA. Finalmente, el diseño de la realización antes mencionada permite definir y ensayar una metodología de prototipado rápido para sistemas en un chip. Esta lectura resultará de utilidad a todos aquellos ingenieros de diseño relacionados con el mundo de las arquitecturas para la codificación de vídeo. ····· 103612833
für 62.10€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray Las técnicas de diseño de sistemas electrónicos, llamémoslas tradicionales, empiezan a exhibir problemas de escalado cuando se trabaja con circuitos cada vez más complejos. En realidad, ésta es una circunstancia que no es nueva y lleva amenazando con colapsar los actuales modelos de diseño desde hace casi una década. En esta Tesis Doctoral el autor aborda el diseño de sistemas heterogéneos complejos, como por ejemplo son los SoCs (System on Chip), desde una nueva perspectiva y partiendo de la siguiente premisa: `Un SoC comparte muchas características con los sistemas distribuidos heterogéneos en red`. A lo largo del texto, se profundiza un poco más en esta analogía para terminar con la propuesta de un middleware de comunicaciones HW/SW para SoCs: Object Oriented Communication Engine (OOCE). OOCE se basa en el paradigma de objeto distribuido para asegurar la interoperabilidad entre componentes y gestionar de forma uniforme la heterogeneidad. A través de una explicación paso a paso y guiada por ejemplos, se describen la implementación de la arquitectura y servicios que OOCE ofrece, haciendo especial énfasis en los beneficios que aporta al diseño de SoCs. ····· 103611427
für 53.10€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray IP-based design is inevitable, taking into account the complexities of today`s electronic designs. One such IP core that plays an important role in IP-based designs is microprocessor core. Soft processor cores are delivered in RTL code and provide high flexibility for users. This work aims at improving an existing soft microprocessor core optimized for Xilinx Virtex®-4 FPGA, which runs at a very high clock frequency at around 350 MHz, whereas most processor cores released by FPGA vendors run at about 200 MHz. Improvement includes design and implementation of instruction and data caches. Mechanisms to allow non-cacheable memory access are also implemented. Interrupt support and exception handling is added as well, preparing the microprocessor core to host MMU-less operating systems such as uCLinux, and full Linux provided that MMU is also added to the processor core. Thorough verification of the added modules is heavily emphasized in this work. Maintaining core clock frequency at its maximum has been the main concern through all the design and implementation steps. ····· 10361623
für 61.20€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray Run-Time Reconfigurable Instruction Set Processors are next generation processors, which can optimize their instruction sets according to the demands of the applications being under execution on them. This optimization is achieved through reconfiguration in their hardware on fly. In this way the reconfigurable processors adapt their hardware, which is most suitable one for the running application and consequently they enhance the performance. Reconfigurable instruction set processors are the programmable processors that contain the reconfigurable logic in one or more of their functional units. The hardware design of such type of processors can be categorized into two main tasks: The design of reconfigurable logic itself and the design of the communication interface of reconfigurable logic with the remaining modules of the processor. ····· 10361311
für 71.10€ kaufen ···· Rheinberg-Buch.de - Bücher, eBooks, DVD & Blu-ray The rise of multicores has brought the problem of effective concurrent programming to the forefront of computing research, presenting both immense opportunities and enormous challenges. Traditional multithreaded programming models use low-level primitives such as locks to guarantee mutual exclusion and protect shared data. The trade-off between programming ease and performance imposed by locks remains one of the key challenges to programmers and computer architects of the multicore era. Transactional Memory (TM) is a conceptually simpler programming model that can help boost developer productivity by eliminating the complex task of reasoning about the intricacies of safe fine-grained locking. Fast implementations of transactional programming constructs are necessary for TM to gain widespread usage. This book focuses on the hardware mechanisms that provide optimistic concurrency control with stringent guarantees of atomicity and isolation, with the intent of achieving high-performance across a variety of workloads, at a reasonable cost in terms of design complexity. ····· 10361294· 1 ·· 2 ·· 3 ·
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